1 nr102405 hv2701 initial release features hvcmos technology for high performance integrated bleed resistors on the outputs 16 channels of high voltage analog switch 3.3v input logic level compatible 20mhz data shift clock frequency very low quiescent power dissipation-10a low parasitic capacitance dc to 10mhz analog signal frequency -60db typical off-isolation at 5mhz cmos logic circuitry for low power excellent noise immunity cascadable serial data register with latches flexible operating supply voltages applications medical ultrasound imaging ndt metal ? aw detection piezoelectric transducer drivers optical mems modules general description the supertex hv2701 is a low charge injection 16-channel high voltage analog switch integrated circuit (ic) with bleed resistors. the device can be used in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging and piezoelectric transducer drivers. the bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. input data is shifted into a 16-bit shift register that can then be retained in a 16-bit latch. to reduce any possible clock feed through noise, the latch enable bar should be left high until all bits are clocked in. data are clocked in during the rising edge of the clock. using hvcmos technology, this device combines high voltage bilateral dmos switches and low power cmos logic to provide ef? cient control of high voltage analog signals. the device is suitable for various combinations of high voltage supplies, e.g., v pp /v nn : +40v/-160v, +100v/-100v, and +160v/-40v. hv2701 block diagram low charge injection 16-channel high voltage analog switch with bleed resistors le cl d le cl level shifters output switches latches v pp v nn v dd d out d in clk sw0 gnd d le cl d le cl d le cl d le cl sw1 sw2 sw14 sw15 r gnd 16 bit shift register
2 nr102405 hv2701 ordering information device package options 48-lead tqfp (1.4mm) hv2701 HV2701FG-G -g indicates package is rohs compliant (green) absolute maximum ratings v dd logic supply -0.5v to +7v v pp -v nn differential supply 220v v pp positive supply -0.5v to v nn +200v v nn negative supply +0.5v to -200v logic input voltage -0.5v to v dd +0.3v analog signal range v nn to v pp peak analog signal current/channel 3.0a storage temperature -65c to 150c power dissipation 1w *absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. operation conditions symbol parameter value v dd logic power supply voltage 3.0v to 5.5v v pp positive high voltage supply 40v to v nn +200v v nn negative high voltage supply -40v to C160v v ih high level input voltage 0.9v dd to v dd v il low level input voltage 0v to 0.1v dd v sig analog signal voltage peak-to-peak v nn +10v to v pp -10v t a operating free air temperature 0c to 70c notes: 1 power up/down sequence is arbitrary except gnd must be powered-up ? rst and powered-down last. 2 v sig must be within v nn and v pp or ? oating during power up/down transition. 3 rise and fall times of power supplies v dd , v pp , and v nn should not be less than 1.0msec.
3 nr102405 hv2701 sym parameter 0c +25c +70c units conditions min max min typ max min max r ons small signal switch on-resistance 30 26 38 48 ? i sig = 5ma v pp = +40v v nn = -160v 25 22 27 32 i sig = 200ma 25 22 27 30 i sig = 5ma v pp = +100v v nn = -100v 18 18 24 27 i sig = 200ma 23 20 25 30 i sig = 5ma v pp = +160v v nn = -40v 22 16 25 27 i sig = 200ma ?r ons small signal switch on-resistance matching 20 5.0 20 20 % i sig = 5ma, v pp = +100v, v nn = -100v r onl large signal switch on-resistance 15 ? v sig =v pp -10v, i sig =1a r int value of output bleed resistor 20 35 50 k? output switch to rgnd i rint = 0.5ma i sol switch off leakage per switch* 5.0 1.0 10 15 a v sig = v pp -10v and v nn +10v v os dc offset switch off* 300 100 300 300 mv no load dc offset switch on* 500 100 500 500 mv i ppq quiescent v pp supply current 10 50 a all switches off i nnq quiescent v nn supply current -10 -50 a all switches off i ppq quiescent v pp supply current 10 50 a all switches on, i sw = 5ma i nnq quiescent v nn supply current -10 -50 a all switches on, i sw = 5ma i sw switch output peak current 3.0 3.0 2.0 2.0 a v sig duty cycle < 0.1% f sw output switching frequency 50 khz duty cycle = 50% i pp average v pp supply current 6.5 7.0 8.0 ma v pp = +40v v nn = -160v all output switches are turning on and off at 50khz with no load. v pp = +100v v nn = -100v 4.0 5.5 5.5 v pp = +160v v nn = -40v 4.0 5.0 5.5 i nn average v nn supply current 6.5 7.0 8.0 ma v pp = +40v v nn = -160v v pp = +100v v nn = -100v 4.0 5.0 5.5 v pp = +160v v nn =-40v 4.0 5.0 5.5 i dd average v dd supply current 4.0 4.0 4.0 ma f clk = 5mhz, v dd = 5.0v i ddq quiescent v dd supply current 10 10 10 a all logic inputs are static i sor data out source current 0.45 0.45 0.70 0.40 ma v out = v dd -0.7v i sink data out sink current 0.45 0.45 0.70 0.40 ma v out = 0.7v c in logic input capacitance 10 10 10 pf dc electrical characteristics (over recommended operating conditions unless otherwise noted) * see test circuits on page 5
4 nr102405 hv2701 ac electrical characteristics (over recommended operating conditions, v dd = 5.0v, t r = t f 5ns, 50% duty cycle, c load = 20pf unless otherwise noted) sym parameter 0c +25c +70c units conditions min max min typ max min max t sd set up time before le rises 25 25 25 ns t wle time width of le 56 56 56 ns v dd = 3.0v 12 12 12 v dd = 5.0v t do clock delay time to data out 50 100 50 78 100 50 100 ns v dd = 3.0v 15 40 15 30 40 15 40 v dd = 5.0v t wcl time width of cl 55 55 55 ns t su set up time data to clock 21 21 21 ns v dd = 3.0v 777v dd = 5.0v t h hold time data from clock 22 2nsv dd = 3.0 or 5.0v f clk clock frequency 888 mhz v dd = 3.0v 20 20 20 v dd = 5.0v t r ,t f clock rise and fall times 50 50 50 ns t on turn on time* 5.0 5.0 5.0 s v sig = v pp -10v, r load = 10k? t off turn off time* 5.0 5.0 5.0 s v sig = v pp -10v, r load = 10k? dv/dt maximum v sig slew rate 20 20 20 v/ns v pp = +40v, v nn = -160v 20 20 20 v pp = +100v, v nn = -100v 20 20 20 v pp = +160v, v nn = -40v k o off isolation* -30 -30 -33 -30 db f = 5.0mhz, 1k?//15pf load -58 -58 -58 f = 5.0mhz, 50? load k cr switch crosstalk* -60 -60 -70 -60 db f = 5.0mhz, 50? load i id output switch isolation diode current 300 300 300 ma 300ns pulse width, 2.0% duty cycle c sg(off) off capacitance sw to gnd 5.0 17 5.0 12 17 5.0 17 pf 0v, f = 1.0mhz c sg(on) on capacitance sw to gnd 25 50 25 38 50 25 50 pf 0v, f = 1.0mhz +v spk output voltage spike* 150 mv v pp = +40v, v nn = -160v, r load = 50ohm -v spk +v spk 150 v pp = +100v, v nn = -100v, r load = 50ohm -v spk +v spk 150 v pp = +160v, v nn = -40v, r load = 50ohm -v spk qc charge injection* 820 pc v pp = +40v, v nn = -160v, v sig = 0v 600 v pp = +100v, v nn = -100v, v sig = 0v 350 v pp = +160v, v nn = -40v, v sig = 0v * see test circuits on page 5
5 nr102405 hv2701 hv2701 test circuits dd pp pp v pp -10v dd pp pp dd pp pp dd pp pp pp pp dd dd pp pp dd pp pp dd pp pp v pp -10v switch off leakage per switch dc offset switch on/off turn (ton/toff) on/off time off isolation output switch isolation diode current switch crosstalk q = 1000pf x v out charge injection output voltage spike r gnd r gnd r gnd r gnd r gnd r gnd r gnd r gnd open
6 nr102405 hv2701 logic function table input data output switch latch enable clock notes: 1. th 16 switches operate independently. 2. serial data is clocked in on the l to h transition of the clk. 3. all 16 switches go to a state retaining their latched condition at the rising edge of le. when le is low the shift registers data ? ow through the latch. 4. d out is high when data in the register 15 is high. 5. shift registers clocking has no effect on the switch states if le is high. 6. the cl clear input overrides all other inputs. logic timing waveforms data in le clock data out off on out (typ ) v 50% 50% 50% 50% t wle t sd t su t h 50% 50% t off 50% t do t on t wcl clr d nC1 d n d n+1 50% 50% 90% 10%
7 doc.# dsfp - hv2701 nr102405 hv2701 pin name tqfp-48 sw4b 3 sw4a 4 sw3b 5 sw3a 6 sw2b 7 sw2a 8 sw1b 9 sw1a 10 sw0b 11 sw0a 12 v nn 13 v pp 15 gnd 17 v dd 18 d in 19 clk 20 le 21 clr 22 d out 23 rgnd 24 sw15b 25 sw15a 26 sw14b 27 sw14a 28 sw13b 29 sw13a 30 sw12b 31 sw12a 32 sw11b 33 sw11a 34 sw10b 37 sw10a 38 sw9b 39 sw9a 40 sw8b 41 sw8a 42 sw7b 43 sw7a 44 sw6b 45 sw6a 46 sw5b 47 sw5a 48 nc 1,2,14,16,35,36 pin con? guration and package outline - 48-lead tqfp (1.4mm) (fg) bsc 0 ? 7 0.354 0.01 (8.992 0.254) 0.275 0.004 (6.985 0.102) 0.008 0.003 (0.2032 0.0762) 0.020 (0.508) 0.055 0.004 (1.397 0.102) 0.039 (0.991) 0.059 0.004 (1.498 0.102) 0.354 0.01 (8.992 0.254) 0.024 0.008 (0.610 0.203) 0.275 0.004 (6.985 0.102) measurement legend = dimensions in inches dimensions in millimeters pin 1 pin 12 nc = no internal connection.
|
